英国诺丁汉大学对CCD和CMOS的研究
时间:2012-12-17 18:36:00 来源:www.ukthesis.org 作者：英国论文网 点击:118次
UNIVERSITY of NOTTINGHAM
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
HDL FOR PROGRAMMABLE LOGIC WITH PROJECT
MODULE CODE: H64HPP
Project – ADC Controller Core Design
1 INTRODUCTION
两个最广泛部署图像的是传感器技术中的CCD（电荷耦合器件）和CMOS（互补金属氧化物半导体）。众所周知CCD相机提供更高的图像质量，但读出速度较低。相反，较目前的CMOS摄像头，CCD摄像头，ACD技术稍微降低了图像质量。
The two most widely deployed image sensor technologies are CCD (charge coupled device) and
CMOS (complementary metal oxide semiconductor). It is well known that the CCD camera offers
higher image quality, but suffers from lower read-out speed. On the contrary, compared with the
CCD camera, the current CMOS camera technology has slightly lower image quality. However, the
CMOS camera enjoys high-speed random access to the image pixels of interest which means that
data can be rapidly transferred to a digital signal processor.
One of the research projects we are investigating is http://www.ukthesis.org/ygsslwdx full-field laser Doppler blood flowmetry, in
which an in-house designed CMOS camera route has been followed. Such an approach offers high-
speed random access to individual pixels.
Fig.1 The data acquisition system for the 32x32 full field laser Doppler blood flowmetry
我们已经开发了一个研究大小为32x32像素的CMOS摄像头芯片激光多普勒血流仪监测。在该芯片中，为了减少模拟输出采用32的数目，而不是采用1024个模拟输出模拟输出，其中32像素共用一个模拟量输出。
We have developed a CMOS camera chip of size of 32x32 pixels for the research of full-field
laser Doppler blood flowmetry. In this chip, in order to reduce the number of analogue outputs, 32
analogue outputs rather than 1024 analogue outputs are adopted, in which 32 pixels share one
analogue output. Conventional laser Doppler systems usually require a sampling frequency of at
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least 40KHz for each pixel, and hence a sample rate of 40MSPS (Mega Samples Per Second) is
required for the CMOS camera chip of 32x32 pixels if a single ADC channel is used. In addition,
the low modulation depths (~1%) of laser Doppler blood flow signals means that a high number of
bits are usually required. Therefore, a single channel ADC module with high-speed (1-170MSPS)
and high-resolution (14 bits) has been developed based on TI ADS5545 [1]. The entire prototyping
system as shown in Fig.1, consists mainly of the 32x32 pixel CMOS camera chip, a single channel
ADS5545 based ADC module and Xilinx Spartan-3E FPGA device (XC3S500E-FG320-5 [2]),
which is not only used to implement required real-time data-processing algorithm (e.g. FFT
processing), but also used as a microcontroller to control both the CMOS camera chip and the ADC
module.
2 PROJECT DESCRIPTION
You are asked to develop (write, simulate) an ADC controller core as shown in Fig.1 and
implement the core on Xilinx Spartan-3E FPGA device, XC3S500E-FG320-5 [2]. In this ADC
controller core, the following two key functions must be implemented.
ADC sampling: It can be seen from Fig.1 that the ADC controller core sends the address signals,
ROW (5 bits) and COL (5 bits) to enable a particular pixel to be sampled by the ADC module
through a digital 5-to-32 decoder and an analogue 32-to-1 multiplexer. For example, if signals,
ROW and COL, are “01111” and “10101”, respectively, the pixel at the 15th row and 21st column
is going to be routed to the analogue input of the ADC module. On the other hand, it can also be
known from Fig.2, which is taken from the Figure 1 in the ADS5545 datasheet [1] that there is a
sampling latency of 14 cycles. In the ADS5545 based ADC module, the differential clock (Input
Clock as shown in the Figure 1 in the ADS5545 datasheet) is generated from the single-end clock,
CLKIN, via a RF transformer. In terms of CLKIN, the ADC sampling happens at the rising edge of
CLKIN rather than at the falling edge of CLKIN. Furthermore, you must use CLKOUT to clock out
the digital sampled data since the rising edge of CLKOUT perfectly matches the digital sampled
data.
Fig.2 Timing diagram for ADS5545 sampling
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ADC configuration: You MUST use serial interface programming only (Fig.3) to configure the
following serial registers as required:
1) Serial register B: Straight binary, Low SPEED mode and Normal operation
2) Serial register C: Normal operation
3) Serial register G: Parallel CMOS outputs
4) Serial register H: Internal reference and Power Mode 3
Fig.3 Serial programming interface timing diagram
NOTE: Please read the relevant parts of the ADS5545 datasheet very carefully to
ensure that you fully understand the timing of the signals related to ADS5545
sampling and configuration.
The specific design requirements of the ADC controller core are as follows:
To facilitate the assessment of your ADC controller core design, you must use the following
entity declaration for the top level design.
-- Required entity declaration
entity AdcController is
port(
-- Interface signals with other modules inside of the FPGA
Reset, Clock40M, Start: in std_logic;
DataReady: out std_logic;
ReadAddress: in std_logic_vector (9 downto 0);
ReadEnable: in std_logic;
ReadClock: in std_logic;
ReadData: out std_logic_vector (13 downto 0);
-- Interface signals with the ADS5545 based ADC module
CLKIN: out std_logic;
CLKOUT: in std_logic;
D: in std_logic_vector (13 downto 0);
SEN, SDATA, SCLK: out std_logic;
-- Interface signals to address a pixel in the CMOS camera chip
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ROW, COL: out std_logic_vector (4 downto 0)
);
end AdcController;
You must create a dual port RAM memory [2] component of size of 1024 x 14bits to store
the sampled data using Xilinx core generator, and the component declaration must
-- Required component declaration of the dual port RAM memory
component dpram1024x14
port (
addra: IN std_logic_VECTOR(9 downto 0);
addrb: IN std_logic_VECTOR(9 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(13 downto 0);
doutb: OUT std_logic_VECTOR(13 downto 0);
enb: IN std_logic;
wea: IN std_logic);
end component;
NOTE: Please refer to VHDL Lab on how to create a dual port RAM IP core in
Xlinx ISE design environment.
The sampled data storage must be:
With the arrangement of the sampled data storage as above, in your design, you can simply
connect some of the interface signals to the memory component as follows:
ReadAddress -> addrb
ReadEnable -> enb
ReadClock -> clkb
ReadData -> dout
The description of interface signals:
Signal Description
Reset Active high, to reset the ADC controller core. Whenever issued,
it lasts 25 nanosecond, or one cycle (40MHz)
Clock40M 40MHz clock, the main clock for the ADC controller
Start Active high, to start the ADC controller core, Whenever issued,
it lasts 25 nanosecond, or one cycle (40MHz)
DataReady Active high, to indicate that one frame sampled data have been
written into the dual port RAM via port A and can be read out#p#分页标题#e#
from part B. DataReady must last 25 nanosecond, or one cycle
(40MHz)
ReadAddress Read address signal of the dual port RAM memory
ReadEnable Active high, to enable read operation for the dual port RAM
memory
ReadClock Read clock signal for the dual port RAM memory
ReadData Whenever the ReadEnable signal is high at the rising edge of the
ReadClock, the sampled data pointed by ReadAddress at the
same edge will appear at ReadData immediately after the same
edge
CLKIN The sampling clock to the ADC module
CLKOUT The output clock from the ADC module, which is perfectly
aligned to the output data, D
D The output data from the ADC module
SEN, SDATA, SCLK ADC configuration signals
ROW, COL Addresses signals to pixel
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3 DESIGN TOOLS
The project design tools are Xilinx ISE 10.1 and Mentor Graphics ModelSim SE 6.3h, which are
available in the 4th floor computer lab (402) during working hours. Alternatively, for those of you
page below:
http://www.xilinx.com/tools/webpack.htm
However, if you go for ISE WebPACK 10.1, then you have to use ISE simulator.
4 PROJECT WRITE UP
The ADC controller core design must be submitted to the coursework drop box in the ESLC
(Engineering and Science Learning Centre) atrium with a report of no longer than 20 pages
(excluding Appendices) and two CDs containing your VHDL code (one disc a duplicate of the
other) by 3:00pm, Tuesday, 17th January 2012. You must date and sign to indicate that you have
submitted your report.
The report should consist of the following:
Introduction
A description of the ADC controller core design
Diagrams of the ADC controller core design, in which the interface signals between
components are labelled
Explain each VHDL code (VHDL design and testbench)
Show simulation (behavioural and post-route) results (waveforms) with a brief explanation
FPGA implementation results, in terms of resource usages
Discussion and Conclusions
Appendix that must include all VHDL codes and any other items you feel are necessary
NOTE: A penalty of 5% per working day will be imposed for the late submission.
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